In order to reduce the on-resistance of a power MOSFET (metal-oxide-semiconductor field-effect transistor), a trench gate structure (U-MOS structure) with a gate electrode buried in a semiconductor substrate has been proposed. In the U-MOS structure, a plurality of gate trenches are periodically formed in the upper surface of the semiconductor substrate. A gate electrode is buried in this gate trench. Thus, the region of the semiconductor substrate between the gate trenches is brought into contact with a source electrode. Accordingly, the source layer and the carrier ejection layer connected to the source electrode need to be formed in the region between the gate trenches. Here, the source layer needs to be formed near the gate trench, and the carrier ejection layer needs to be formed in a region spaced from the gate trench. Furthermore, among a plurality of MOSFETs formed in one chip, the distance between the carrier ejection layer and the gate trench needs to be made uniform so that the characteristics such as threshold and on-resistance are made uniform.
On the other hand, in improving the performance of the power MOSFET, increasing the integration density of the U-MOS structure is effective. However, the increase of integration density of the U-MOS structure is restricted by the limit of alignment accuracy between the gate trench and the carrier ejection layer.